Chapter 7.PDF

In Chapter 6 we learned that oblivious unitand multi-delay simulation may require several gate simulations to be performed for a single gate. These extra gate-simulations significantly increase simulation time over oblivious zero-delay simulation. The Parallel Technique was introduced as a method of speeding up these additional gate simulations. Chapter 2 introduced the concept of bit-parallel simulation, using the extra bits in a word to perform useful work. The Parallel Technique uses bit-parallel simulation in a more sophisticated way to perform the additional gate simulations required by unit-delay and multi-delay simulation. Rather than treating a word as a simple collection of bits, the parallel technique indexes each bit in a word, starting on the right with index 0. Figure 7-1 illustrates this indexing, assuming that a word contains eight bits. A longer word will have a correspondingly larger number of indices. Each index corresponds to one unit of simulated time. Bit zero corresponds to time zero, bit one corresponds to time one, and so forth. As in Event-Driven Simulation, these time units are of unspecified length, and are assumed to occur during the processing of a single input vector.